A desired logic circuit may be produced by writing of functions of logic macros and interconnections among the logic macros into a field-programmable gate array (FPGA). With improvement in circuit integration levels and operating frequencies of FPGAs in recent years, applications have been contrived in which FPGAs are made to execute operational processing executed conventionally by central processing units (CPUs). Thus processing performance of operational processing systems may be improved.
In case where an FPGA is made to execute operational processing executed conventionally by a CPU, processing performance may be further improved by provision of a plurality of identical operational circuits in the FPGA and execution of operations in parallel by the operational circuits. A number of the operational circuits that execute the operations in parallel may be referred to as parallelism or parallel number.
There have been known a parallel computing controller that adjusts parallelism for each job so that all jobs may complete at the same time and a parallel processing apparatus that processes operations for data divided by processing unit with use of a plurality of processors.
Related arts are disclosed in Japanese Laid-open Patent Publication No. 2013-140490 and Japanese Laid-open Patent Publication No. 2010-277579.